型號 封裝 在線定購
LPC1313FBD48(查看) LQFP48
LPC1313FHN33(查看) HVQFN33


技術資料—— LPC1313 PDF技術資料
LPC1313 參數
LPC1313 存儲器
Flash (KB) 32
RAM (kB) 8
LPC1313 其他參數
fmax (MHz) 72
I/Opins 28-42
I2C 1
I2S -
定時器 5
PWM 11
I/O 電壓 (V) 3.3
CPU 電壓 (V) 3.3
LPC1313 封裝與引腳

LPC1313 概述

The LPC1313 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.

The LPC1313 operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

LPC1313 特性

  • ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.
  • ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
  • 32 kB on-chip flash programming memory.
  • 8 kB SRAM.
  • In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
  • Serial Wire Debug and Serial Wire Trace port
  • High-current output driver (20 mA) on one pin
  • High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus
  • Three reduced power modes: Sleep, Deep-sleep, and Deep power-down
  • Single power supply (2.0 V to 3.6 V).
  • 10-bit ADC with input multiplexing among 8 pins
  • Integrated oscillator with an operating range of 1 MHz to 25 MHz.
  • Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.
  • Serial interfaces:
    • UART with fractional baud rate generation, modem, internal FIFO, and RS-485/EIA-485 support.
    • SSP controller with FIFO and multi-protocol capabilities
    • Additional SSP controller on LPC1313FBD48/01
    • I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode
  • Other peripherals:
    • Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
    • Four general purpose counter/timers with a total of four capture inputs and 13 match outputs.
    • Programmable WatchDog Timer (WDT).
    • System tick timer.

捕鱼大师官方网 简单的二人扑克牌玩法 香港九龙心水最准资料128 重庆时时彩乐娱网址 体育彩票任选9场胜负19069期 vr赛哪里的 辽宁福彩12选开奖 福彩3d软件官方下载 赠彩金的app 快乐十分追号方案 三分时时彩正规吗